1. Field of the Invention
The present invention generally relates to phase lock loops.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “logical signal,” “clock,” “rising edge,” “phase,” “capacitor,” “charge,” “charge pump,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “source,” “gate,” “drain,” “circuit node,” “ground node,” “operational amplifier,” “common-mode feedback,” “electrical potential,” “switch,” “single-ended circuit,” and “differential circuit.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.
Through this disclosure, a logical signal is a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal.
A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low.
A clock signal is a cyclic logical signal. For brevity, hereafter, “clock signal” may be simply referred to as “clock.”
A timing of a clock signal refers to a time instant where the clock signal undergoes a transition of state, either a low-to-high transition or a high-to-low transition. When a clock signal undergoes a low-to-high (high-to-low) transition, a rising (falling) edge is observed in a timing diagram.
A phase lock loop (PLL) receives a first clock and outputs a second clock such that a phase of the second clock tracks a phase of the first clock. As a result, a frequency of the second clock is determined by a frequency of the first clock. A prior art phase lock loop comprises a phase/frequency detector (hereafter PFD), a charge pump (hereafter CP) circuit, a loop filter (hereafter LF), a voltage-controlled oscillator (hereafter VCO), and a clock divider circuit, wherein: the VCO outputs the second clock in accordance with a control voltage such that the frequency of the second clock is determined by the control voltage, the clock divider circuit receives the second clock and outputs a third clock in accordance with a division ratio, the PFD receives the first clock and the third clock and outputs a timing signal representing a difference in timing between the first clock and the third clock, the CP circuit converts the timing signal into a current signal, the LF filters the current signal to establish the control voltage to control the frequency of the second clock. The frequency of the second clock is thus adjusted in a closed loop manner to track a frequency of the first clock. “Phase/frequency detector,” “charge pump circuit,” “loop filter,” “voltage-controlled oscillator,” and “clock divider circuit” are all well known in the prior art and thus not described in detail here. In a steady state, the frequency of the second clock is equal to the frequency of the first clock multiplied by a multiplication factor N that can be expressed asN=Nint+αwhere Nint is a positive integer and a is a rational number smaller than 1 (one) but not smaller than 0 (zero). If α is zero, the clock divider circuit has a fixed division factor Nint, i.e. it performs a “divide by Nint” function wherein one cycle of the third clock is output for every Nint cycles of the second clock. If a is nonzero, it must be a fractional number; in this case, the phase lock loop is referred to as “fractional-N PLL,” and the clock divider circuit cannot have a fixed division factor. In an embodiment, the division factor of the clock divider circuit is modulated by a delta-sigma modulator and dynamically toggle between Nint and Nint+1 such that a mean value of the division factor is equal to Nint+α. Since the value of the division factor is modulated, an instantaneous value differs from a mean value of the division factor (e.g., Nint and Nint+1 are different from Nint+α), resulting in an instantaneous noise additive to the PLL. In U.S. Pat. No. 7,999,622, Galton et al disclosed a method to cancel the additive noise resulting from the modulation of the division factor. The method is based on using a digital-to-analog converter to output a current that offsets an additive noise in the output of the charge pump circuit (resulting from the modulation of the division factor). The digital-to-analog converter (DAC), however, contributes thermal noise. To reduce the thermal noise contribution, a large current can be used at the cost of high power consumption. Besides, in practice the DAC is not perfectly linear, and its nonlinearity can contribute additional noise to PLL. To reduce the adverse effect of the nonlinearity of the DAC, a dynamic element matching can be used at the cost of high circuit complexity.
What is disclosed is a method for cancelling a noise in a fractional-N PLL resulting from a modulation of a division factor without consuming high power or demanding high circuit complexity.